In current flip-chip technology, there are electrode pads on an active face of a semiconductor chip in an integrated circuit (IC), while there are electrically connecting pads corresponding to the electrode pads on an organic circuit board. Solder structures or other conductive adhesives are formed between the electrode pads of the semiconductor chip and the electrically connecting pads of the circuit board, such that they provide electrical and mechanical connection therebetween. Related manufacturing processes are illustrated in FIGS. 1A to 1F as follows.
Referring to FIG. 1A, a circuit board 11 with a plurality of electrically connecting pads 111 and circuits 112 on one surface thereof is provided.
Referring to FIG. 1B, an insulating protective layer 12 is formed on the surface of the circuit board 11 that has the electrically connecting pads 111 by printing, spin coating or adhesion etc. The insulating protective layer 12 is patterned to form openings 120 in order to expose a portion of the upper surfaces of the electrically connecting pads 111.
Referring to FIG. 1C, a conductive layer 13 is formed on the insulating protective layer 12 and the openings 120, which is essentially used as an electrical conduction path in subsequent electroplating of the soldering materials.
Referring to FIG. 1D, a resist layer 14 is formed on the conductive layer 13 and patterned to have openings 140 therein for exposing the openings 120 of the insulating protective layer 12.
Referring to FIG. 1E, an electroplating process is performed on the circuit board 11. Owing to the conductive property of the conductive layer 13 which acts as an electrical conduction path during electroplating, electroplated conductive posts 15 can be formed in the openings 140 and 120. The tops of the electroplated conductive posts 15 exceed the openings 120 and form wings 151 in the openings 140.
Referring to FIG. 1F, the resist 14 and the underlying conductive layer 13 are removed such that the electroplated conductive posts 15 form projected wings 151 on the surface of the insulating protective layer 12.
However, in the above prior-art manufacturing processes, the sizes of the openings 120 and 140 are very small, usually around 50 μm to 60 μm, alignment is not easy. In order for the openings 140 to align with the openings 120, the size of the openings 140 is usually increased to reduce the difficulty in alignment and increase alignment precision. As the aperture of the openings 120 is getting even smaller, due to the limitation of machines, the size of the openings 140 may be much larger than that of the openings 120 or even twice as large.
The enlargement of the aperture of the openings 140 may result in wings 151 formed on the electroplated conductive posts 15. As a result, intervals between the electroplated conductive posts 15 have to increase, which hinders the formation of fine-pitch pre-soldering bumps to be formed on the electroplated conductive posts 15.
Moreover, since the wings 151 of the electroplated conductive posts 15 are projected from the insulating protective layer 14, they tend to experience detrimental stresses due to temperature variation and difference in coefficient of thermal expansion (CTE), especially between the electroplated conductive posts 15 and the wings 151.
Therefore, there is a need for a semiconductor package circuit board and a manufacturing method thereof that allow the formation of fine-pitch electroplated conductive posts on the electrically connecting pads of the substrate.